LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY TURN2_10 IS
PORT(A:IN STD_LOGIC_VECTOR(4 DOWNTO 0);
B:OUT INTEGER RANGE 0 TO 32);
END;
ARCHITECTURE ART OF TURN2_10 IS
BEGIN
B<=CONV_INTEGER(A);
END;
匿名回答于2024-05-25 18:32:00
