EDA实验数据分配器VHDL程序设计，设有复位信号RST实现选中信道数据输出到数据Dout？

LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYselect1_8ISPORT(Q:INSTD_LOGIC_VECTOR(3DOWNTO0);sel:INSTD_LOGIC_VECTOR(2DOWNTO0);D0,D1,D2,D3,D4,D5,D6,D7:OUTSTD_LOGIC_VECTOR(3DOWNTO0))

;ENDselect1_8;ARCHITECTUREabcOFselect1_8ISBEGINPROCESS(sel)BEGINCASEselISWHEN"000"=>D0<=Q;WHEN"001"=>D1<=Q;WHEN"010"=>D2<=Q;WHEN"011"=>D3<=Q;WHEN"100"=>D4<=Q;WHEN"101"=>D5<=Q;WHEN"110"=>D6<=Q;WHENOTHERS=>D7<=Q;ENDCASE;ENDPROCESS;ENDabc;

匿名回答于2024-05-25 18:43:38