library ieee;use ieee.std_logic_1164.all;entity sreg8b is port(clk,rst:in std_logic; load,en:in std_logic; din:in std_logic_vector(7 downto 0)
; qb:out std_logic)
;end sreg8b;architecture behan of sreg8b is signal reg8:std_logic_vector(7 downto 0)
; begin process(clk,rst,load,en) begin if(rst='1'
)then reg8
匿名回答于2024-05-25 18:36:31
